Plasma display panel and method of driving the same

ABSTRACT

Provided is a method of driving a plasma display panel (PDP) that comprises X electrodes, Y electrodes, and address electrodes, wherein a frame, which is a display cycle, comprises a plurality of subfields for time-divisional gray scale display. Each of the subfields includes a reset period, an address period, and a sustain period. The reset period is one of a main reset period during which both a rising pulse and a falling pulse are applied to the Y electrodes and an auxiliary reset period during which one of the rising pulse and the falling pulse is applied to the Y electrodes, and the main reset period comprises a first pulse time during which a pulse rising to a level of a first voltage and then falling to a level of a second voltage is applied to the Y electrodes and a second pulse time during which a pulse rising to a level of a third voltage and then falling to a level of a fourth voltage is applied to the Y electrodes.

CLAIM OF PRIORITY

This application makes reference to, incorporates the same herein, andclaims all benefits accruing under 35 U.S.C. §119 from an applicationearlier filed in the Korean Intellectual Property Office on the 12 Apr.2007 and there duly assigned Serial No. 10-2007-0036179.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a plasma display panel (PDP) and amethod of driving the PDP, and more particularly, to a PDP capable ofreducing the generation of an erroneous discharge and a method ofdriving the PDP.

2. Description of the Related Art

PDPs, which have become popular as large-size flat display panels, aredevices that display desired images by applying a discharge voltage to adischarge gas between two substrates with a plurality of electrodesformed on the substrates so as to generate ultraviolet (UV) rays, andexciting a patterned phosphor material with the UV rays.

In general, a PDP is driven according to a unit frame, which is adisplay cycle divided into a plurality of subfields, and a gray scale isrepresented by a combination of subfields. Each of the sub fieldsincludes a reset period, an address period, and a sustain period. Duringa reset period, wall charges formed by a sustain discharge generatedduring a previous period are erased, and wall charges are set up inorder to perform the next address discharge. During an address period,cells of the PDP that are to be turned on are discriminated from cellsthat are to be turned off, and wall charges are accumulated on theto-be-turned-on cells (i.e., addressed cells). During a sustain period,a sustain discharge for actually displaying an image on the addressedcells is performed.

During a reset period of each subfield, a rising ramp portion of a resetpulse is applied to Y electrodes in order to thereby generate a weakdischarge, and a falling ramp portion of the reset pulse is then appliedto the Y electrodes in order to equalize the wall charge conditions ofall of the cells of the PDP. However, no sustain discharge is generatedin cells that were not selected in the previous subfield, so that thewall charge states of the unselected cells set up during the resetperiod of the previous subfield are kept. In other words, there is noneed to re-accumulate wall charges during the reset period of thecurrent subfield by applying a rising ramp portion.

Hence, a main reset pulse having both a rising ramp portion and afalling ramp portion may be applied during the reset period of a firstsubfield, and then an auxiliary reset pulse having either a rising rampportion or a falling ramp portion may be applied during the resetperiods of a predetermined number of subfields other than the firstsubfield.

However, a strong discharge is caused by a relatively large number ofpriming particles that are generated during a main reset period when arapid pattern change occurs, so that an erroneous discharge, in which asustain discharge occurs even when no data is applied during an addressperiod, may occur. Moreover, in a low-gray-level subfield, an erroneousdischarge is generated during a reset period, and thus even when data isapplied to discharge cells during an address period, the correspondingdischarge cells are not turned on, so that no discharge is generatedduring a sustain period, resulting in a low discharge. Some of thedischarge cells turned on during the current subfield do not undergodischarge during a sustain period of the current subfield, but instead,the sustain discharge occurs in the next subfield, so that alow-gray-level erroneous discharge is generated.

SUMMARY OF THE INVENTION

The present invention provides a plasma display panel (PDP) capable ofpreventing the generation of an undesired discharge by removing an errorthat may be generated during a reset operation and also a PDP capable ofpreventing a low discharge and an erroneous discharge in low-gray-levelsubfields, and a method of driving the PDP.

According to an aspect of the present invention, there is provided amethod of driving a plasma display panel (PDP), which comprises Xelectrodes, Y electrodes, address electrodes, and discharge cells togenerate light. The method includes steps of applying a main reset pulseto the Y electrodes during a main reset period of a subfield to resetthe discharge cells, applying an address data signal to the addresselectrodes during an address period to select discharge cells to beturned on, and alternatively applying a sustain pulse to the Xelectrodes and to the Y electrodes during a sustain period to generate asustain discharge in the selected discharge cells. The step of applyingthe main reset pulse further includes steps of applying a pulse risingto a level of a first voltage and then falling to a level of a secondvoltage during a first pulse time period, and applying a pulse rising toa level of a third voltage and then falling to a level of a fourthvoltage during a second pulse time period. The first voltage may belower than the third voltage.

The step of applying the main reset pulse may further include applying apulse falling to a level of a fifth voltage during a preset time periodthat is included in the main reset period. The magnitude of the fifthvoltage may be substantially the same as the magnitude of the fourthvoltage.

The step of applying a pulse rising to the level of the first voltageand then falling to the level of the second voltage may include applyinga pulse rising to the level of the first voltage from a level of areference voltage. The step of applying a pulse rising to the level ofthe first voltage and then falling to the level of the second voltagemay include applying a pulse falling to the level of the second voltagefrom the level of the reference voltage. The step of applying a pulserising to the level of the third voltage and then falling to the levelof the fourth voltage may include applying a pulse rising to the levelof the third voltage from a level of a sixth voltage. The step ofapplying a pulse rising to the level of the third voltage and thenfalling to the level of the fourth voltage may include applying thepulse falling to the level of the fourth voltage from the level of thereference voltage.

The method may further include a step of applying an auxiliary resetpulse to the Y electrodes during an auxiliary reset period of anothersubfield to reset the discharge cells. A maximum voltage of theauxiliary reset pulse may be lower than the third voltage.

The step of applying the auxiliary reset pulse may include a step ofapplying a pulse rising to a level of a first auxiliary voltage, or astep of applying a pulse falling to a level of a second auxiliaryvoltage.

The method of driving a PDP may further include steps of applying areference voltage to the address electrodes during the main resetperiod, and applying a seventh voltage to the X electrodes whileapplying a pulse falling to the level of the fourth voltage to the Yelectrodes during the second pulse time period.

The method driving a PDP may further include applying a seventh voltageto the X electrodes during the address period, applying a selectionpulse having a ninth voltage to the Y electrodes during a selection timethat is included in the address period, and applying an eighth voltageto the Y electrodes during a portion of the address period that is notincluded in the selection time. The address data signal includes a datapulse having a reference voltage or a tenth voltage, the phase of thedata pulse synchronizing with the phase of the selection pulse.

The method driving a PDP may further include applying a referencevoltage to the address electrodes during the sustain period. The sustainpulse has the first voltage.

According to another aspect of the present invention, there is provideda plasma display panel device including a plasma display panel and apanel driving unit applying a set of driving signals to the plasmadisplay panel to drive the plasma display panel. The plasma displaypanel includes a first substrate, a second substrate facing the firstsubstrate, X electrodes and Y electrodes disposed between the firstsubstrate and the second substrate, and address electrodes disposedbetween the first substrate and the second substrate. The addresselectrodes cross the X and Y electrodes, and discharge cells are formedat intersections of the address electrodes with the X and Y electrodes.The set of the driving signals includes a main reset pulse applied tothe Y electrodes during a main reset period of a subfield to reset thedischarge cells, an address data signal applied to the addresselectrodes during an address period to select discharge cells to beturned on, and a sustain pulse alternately applied to the X electrodesand to the Y electrodes during a sustain period to generate a sustaindischarge in the selected discharge cells. The main reset pulse includesa first pulse rising to a level of a first voltage and then falling alevel of a second voltage during a first pulse time period, and a secondpulse rising to a level of a third voltage and then falling to a levelof a fourth voltage during a second pulse time period. The first voltageis lower than the third voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings in which likereference symbols indicated the same or similar components, wherein:

FIG. 1 is a perspective view of a structure of a plasma display panel(PDP) that may be driven using a method according to the presentinvention;

FIG. 2 is a cross-section of a unit display cell of the PDP illustratedin FIG. 1;

FIG. 3 is a schematic diagram of a configuration of electrodes of thePDP illustrated in FIG. 1;

FIG. 4 is a schematic block diagram of a plasma display panel devicethat includes an apparatus for driving the PDP illustrated in FIG. 1;

FIG. 5 is a timing diagram illustrating a method of driving the PDPillustrated in FIG.

FIG. 6 is a timing diagram illustrating driving signals applied toelectrodes in a PDP driving method according to an embodiment of thepresent invention; and

FIG. 7 is a timing diagram illustrating driving signals applied toelectrodes in a PDP driving method according to another embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinvention are shown.

FIG. 1 is a perspective view of a structure of a plasma display panel(PDP) 1 that is driven using a method according to an embodiment of thepresent invention. FIG. 2 is a cross-section of a unit display cell ofthe PDP 1 illustrated in FIG. 1.

Referring to FIG. 1 and FIG. 2, A electrodes (i.e., address electrodes)A1 through Am, first and second dielectric layers 102 and 110, Yelectrodes Y1 through Yn, X electrodes X1 through Xn, phosphor layers112, barrier ribs 114, and a MgO protection layer 104 are includedbetween a first substrate 100 and a second substrate 106.

The A electrodes A1 through Am are arranged in a predetermined patternon the second substrate 106. The second dielectric layer 110 covers theA electrodes A1 through Am. The barrier ribs 114 are formed parallel tothe A electrodes A1 through Am on the second dielectric layer 110. Thebarrier ribs 114 define discharge areas of discharge cells and preventoptical interference between discharge cells. The phosphor layers 112include red phosphor layers, green phosphor layers, and blue phosphorlayers that are arranged on portions of the second dielectric layer 110that cover the A electrodes A1 through Am between the barrier ribs 114.A red phosphor layer, a green phosphor layer, and a blue phosphor layerare sequentially arranged, and this configuration repeats.

The X electrodes X1 through Xn and the Y electrodes Y1 through Yn arearranged in a pattern on the first substrate 100 so as to intersect theA electrodes A1 through Am. The intersections establish correspondingdischarge cells. Each of the X electrodes X1 through Xn, for example,Xn, may include a transparent electrode Xna formed of a transparentconductive material, such as Indium Tin Oxide (ITO), and a metalelectrode Xnb for increasing conductivity. Each of the Y electrodes Y1through Yn, for example, Yn, may include a transparent electrode Ynaformed of a transparent conductive material, such as ITO, and a metalelectrode Ynb for increasing conductivity. The first dielectric layer102 is formed on the entire surface of the first substrate 100 so as tocover the X electrodes XI through Xn and the Y electrodes Y1 through Yn.The protection layer 104, such as, a MgO layer, protecting the PDP 1from a strong electrical field, is formed on the entire surface of thefirst dielectric layer 102. A discharge space 108 is filled with a gasfor forming plasma.

A PDP, which is driven by a driving apparatus of the present invention,is not limited to the PDP 1 illustrated in FIG. 1. In other words, thePDP which is driven by the driving apparatus of the present inventionmay be a two-electrode PDP including only two kinds of electrodesinstead of a three-electrode PDP as illustrated in FIG. 1. In addition,PDPs having other various structures may be used, and any PDP issufficient as long as it is driven using a driving method according toan embodiment of the present invention.

FIG. 3 is a schematic diagram of a configuration of electrodes of thePDP 1 illustrated in FIG. 1. Referring to FIG. 3, the Y electrodes Y1through Yn and the X electrodes X1 through Xn are arranged in parallelto each other, and the A electrodes A1 through Am intersect the Yelectrodes Y1 through Yn and the X electrodes X1 through Xn. Areas wherethe Y electrodes Y1 through Yn and the X electrodes X1 through Xnintersect the A electrodes A1 through Am correspond to discharge cellsCe.

FIG. 4 is a schematic block diagram of a plasma display panel devicethat includes an apparatus for driving the PDP 1 illustrated in FIG. 1.Referring to FIG. 4, the apparatus for driving the PDP 1 includes animage processing unit 300, a control unit 302, an address driving unit306, an X driving unit 308, and a Y driving unit 304. The imageprocessing unit 300 generates internal image signals, for example, 8-bitred (R) image data, 8-bit green (G) image data, 8-bit blue (B) imagedata, a clock signal, a vertical synchronization signal, and ahorizontal synchronization signal, by converting an external analogimage signal into a digital signal. The control unit 302 generatesdriving control signals, namely, an address signal SA, a Y drivingcontrol signal SY, and an X driving control signal SX, according to theinternal image signals of the image processing unit 300. The addressdriving unit 306 generates a display data signal by processing theaddress signal SA from among the driving control signals SA, SY, and SXoutput by the control unit 302 and applies the display data signal toaddress electrode lines. The X driving unit 308 processes the X drivingcontrol signal SX from among the driving control signals SA, SY, and SXoutput by the control unit 302 and applies the X driving control signalSX to X electrode lines. The Y driving unit 304 processes the Y drivingcontrol signal SY from among the driving control signals SA, SY, and SXoutput by the control unit 302 and applies the Y driving control signalSY to Y electrode lines.

FIG. 5 is a diagram illustrating a method of driving the PDP 1illustrated in FIG. 1. Referring to FIG. 5, a unit frame may be dividedinto a predetermined number of subfields, for example, 8 subfields SF1through SF8, in order to accomplish time-divisional gray scale display.The subfields SF1 through SF8 are divided into reset periods R1 throughR8, respectively, address periods A1 through A8, respectively, andsustain periods S1 through S8, respectively.

During each of the reset periods R1 through R8, a reset pulse is appliedto the Y electrodes Y1 through Yn, and thus wall charge conditions forall cells are equalized, so that all of the cells are initialized.

During each of the address periods A1 through A8, an address pulse isapplied to the A electrodes, and simultaneously, corresponding scanpulses are sequentially applied to the Y electrodes Y1 through Yn.

During each of the sustain periods S1 through S8, sustain pulses arealternately applied to the Y electrodes Y1 through Yn and the Xelectrodes X1 through Xn, so that a sustain discharge is generated indischarge cells where wall charges are formed during the address periodsA1 through A8.

The brightness of a PDP is proportional to the number of sustaindischarge pulses applied during the sustain periods S1 through S8included in a unit frame. For example, when one frame in which one imageis formed is represented as 8 subfields and 256 gray scales, differentnumbers of sustain pulses may be allocated to the 8 subfields in theratio of 1:2:4:8:16:32:64:128, respectively. For example, in order toobtain a brightness with a 133 gray scale, discharge cells are addressedduring the first subfield SF1, the third subfield SF3, and the eighthsubfield SF8, and a sustain discharge is performed.

The number of sustain pulses allocated to each subfield may varyaccording to the weight of each subfield depending on an automatic powercontrol (APC) stage. The number of sustain pulses allocated to eachsubfield may also vary in consideration of gamma characteristics orpanel characteristics. For example, a gray scale allocated to the fourthsubfield SF4 may be lowered from 8 to 6, and a gray scale allocated tothe sixth subfield SF6 may be increased from 32 to 34. In addition, thenumber of subfields that constitute one frame may vary according todesign.

FIG. 6 illustrates time dependent driving signals applied to electrodesaccording to a PDP driving method of an embodiment of the presentinvention. Referring to FIG. 6, a unit frame for driving the PDP 1 isdivided into a plurality of subfields SF, each of which has a resetperiod PR, an address period PA, and a sustain period PS. The resetperiod PR is either a main reset period, during which a main reset pulsethat includes both a rising pulse (a first pulse) and a falling pulse (asecond pulse) are applied to the Y electrodes Y1 through Yn, or anauxiliary reset period, during which either a rising pulse (a firstauxiliary pulse) or a falling pulse (a second auxiliary pulse) isapplied to the Y electrodes Y1 through Yn.

A reset period PRn of a subfield SFn is a main reset period. The mainreset period includes a first pulse time period T1 and a second pulsetime period T2. During the first pulse time period T1, a pulse, whichrises to the level of a first voltage Vs and then falls to the level ofa second voltage Vf, is applied to the Y electrodes Y1 through Yn afterthe last sustain pulse applied during the previous sustain period. Forexample, a voltage having a rising ramp from the level of a referencevoltage Vg to the level of the first voltage Vs is applied to the Yelectrodes Y1 through Yn, and then a voltage having a falling ramp fromthe level of the reference voltage Vg to the level of the second voltageVf is applied to the Y electrodes Y1 through Yn.

During the second pulse time period T2, a pulse, which rises to thelevel of a third voltage Vsch+Vset and then falls to the level of afourth voltage Vnf, is applied to the Y electrodes Y1 through Yn. Forexample, a voltage having a rising ramp from the level of a sixthvoltage Vsch to the level of the third voltage Vsch+Vset is applied tothe Y electrodes Y1 through Yn, and a voltage having a falling ramp fromthe level of the reference voltage Vg to the level of the fourth voltageVnf is applied to the Y electrodes Y1 through Yn.

During the main reset period PRn, the reference voltage Vg is applied tothe address electrodes A1 through Am. When a rising ramp voltage isapplied to the Y electrodes Y1 through Yn, the reference voltage Vg isapplied to the X electrodes X1 through Xn. When a falling ramp voltageis applied to the Y electrodes Y1 through Yn, a seventh voltage Ve maybe applied to the X electrodes X1 through Xn.

While the rising ramp voltage is being applied, a weak discharge isgenerated along the direction of the Y electrodes Y1 through Yn to theaddress electrodes A1 through Am and the X electrodes X1 through Xn. Dueto this weak discharge, negative wall charges are accumulated on the Yelectrodes Y1 through Yn, and positive wall charges are accumulated onthe address electrodes A1 through Am and the X electrodes X1 through Xn.

While the falling ramp voltage is being applied, a weak discharge isgenerated along the direction of the address electrodes A1 through Amand the X electrodes X1 through Xn to the Y electrodes Y1 through Yn dueto a wall voltage formed in the discharge cells. Due to this weakdischarge, wall charges formed on the X electrodes X1 through Xn, the Yelectrodes Y 1 through Yn, and the address electrodes A1 through Am arepartially erased, so that the discharge cells are set to have statessuitable for undergoing addressing.

However, when the turned-on states of discharge cells are abruptlychanged to turned-off states like when a pattern change occurs, arelatively large number of priming particles are generated during areset period. Due to the priming particles, a strong discharge insteadof a weak discharge may be generated when a rising ramp voltage and afalling ramp voltage are applied during the reset period. In this case,even when no data pulses are applied during an address period, anerroneous discharge is generated during a sustain period. In particular,when the temperature of a panel, which underwent an aging for a longtime, dropped to a low temperature, a discharge initiation voltage alsodropped. In this case, the frequency of erroneous discharge generationcaused by the strong discharge generated in the reset period wassignificantly increased.

In order to control the priming particles that cause erroneousdischarge, a reset pulse is used twice in a row during a main resetperiod in an embodiment of the present invention. A stable weakdischarge condition is created by inducing a discharge from the firstreset pulse and generating the priming particles. By applying the secondreset pulse, a strong discharge is suppressed, and a proper resetoperation can be executed.

According to an embodiment of the present invention, low-gray-level lowdischarge and low-gray-level erroneous discharge, which are capable ofbeing generated on discharge cells that keep on states, can be reduced.In other words, in a conventional technique, low-gray-level lowdischarge occurs, and even when a data pulse is applied during anaddress period, an addressing operation is not properly performedbecause of an erroneous discharge generated during a reset period priorto the address period, and a discharge is not generated during a sustainperiod. Moreover, in the conventional technique, low-gray-levelerroneous discharge occurs, and some of the discharge cells thatmaintain on states undergo discharge during the sustain period of thenext subfield. However, the use of two reset pulses according to anembodiment of the present invention contributes to a stable resetoperation, so that a low discharge and erroneous discharge generated ata low gray scale can be prevented.

The first voltage Vs is preferably lower than the third voltageVsch+Vset. The second voltage Vf is preferably higher than the fourthvoltage Vnf. In other words, the rising top level voltage of a firstreset pulse of the two reset pulses is preferably lower than the risingtop level voltage of a second reset pulse, and the falling bottom levelvoltage of the first reset pulse of the two reset pulses is preferablyhigher than the falling bottom level voltage of the second reset pulse.

When two reset pulses having an identical size are used, a problem mayarise in that background brightness increases compared with aconventional technique. This problem can be solved by controlling therelative sizes of the voltages as described above.

During an address period PAn, discharge cells in which a sustaindischarge is to occur during a sustain period PSn are selected. Duringthe address period PAn, the seventh voltage Ve is continuously appliedto the X electrodes X1 through Xn, scan pulses are sequentially appliedto the Y electrodes Y1 through Yn, and a display data signal is appliedto the address electrodes A1 through Am in synchronization with the scanpulses so that an address discharge is executed. Each of the scan pulsesfirst has an eighth voltage Vscl+Vsch and then has a ninth voltage Vsclthat is lower than the eighth voltage Vscl+Vsch. The display data signal(or address data signal) has a positive tenth voltage Va synchronizedwith an application of the ninth voltage Vscl of a scan pulse.

In other words, a selection pulse having a ninth voltage is applied tothe Y electrodes during the address period. The selection pulse has afinite pulse width that is defined as a selection time. The eighthvoltage is applied to the Y electrodes during the rest of the addressperiod except the selection time. The display data signal has datapulses having the tenth voltage Va or the reference voltage. Some of thedata pulses may have the tenth voltage and the other data pulses mayhave the reference voltage. The display data signal is applied to theaddress electrodes during the address period. The phase of the datapulses synchronizes with the phase of the selection pulse, andtherefore, address discharge occurs under the combination of the displaydata signal applied to the address electrodes and the synchronizedselection pulse applied to the Y electrodes.

In the discharge cells selected during the address period PAn, a sustaindischarge is generated by a sustain pulse applied during a sustainperiod. On the other hand, in discharge cells that were not selectedduring the address period PAn, sustain discharge is not generated evenwhen a sustain pulse is applied during the sustain period.

During a sustain period PSn, sustain pulses are alternately applied tothe X electrodes X1 through Xn and the Y electrodes Y1 through Yn, sothat a sustain discharge is performed. The brightness of a unit fieldcomprised of a plurality of subfields is displayed by the execution ofsustain discharges depending on gray scale weights allocated to thesubfields. The sustain pulses alternate between the level of the firstvoltage Vs and the level of the reference voltage Vg.

A reset period PRn+1 of the next subfield SFn+1 is an auxiliary resetperiod. During the auxiliary reset period PRn+1, either a rising pulse(a first auxiliary pulse) or a falling pulse (a second auxiliary pulse)is applied to the Y electrodes Y1 through Yn.

Alternatively, both a rising pulse having a rising top level voltagelower than the rising top level voltage of a main reset pulse for a mainreset period and a falling pulse may be applied during the auxiliaryreset period. For example, referring to FIG. 6, both a voltage having arising ramp from the reference voltage Vg to a first auxiliary voltageVas and a voltage having a falling ramp from the level of the referencevoltage Vg to a level of a second auxiliary voltage Vanf may be appliedduring the auxiliary reset period PRn+1. The level of the firstauxiliary voltage Vas can be the same as the level of the first voltageVs, and the level of the second auxiliary voltage Vanf can be the sameas the level of the fourth voltage Vnf. In this case, similar to whenthe main reset pulse is applied, the reference voltage Vg is applied tothe address electrodes A1 through Am. When a rising ramp voltage isapplied to the Y electrodes Y1 through Yn, the reference voltage Vg maybe applied to the X electrodes X1 through Xn. When a falling rampvoltage is applied to the Y electrodes Y1 through Yn, the seventhvoltage Ve may be applied to the X electrodes X1 through Xn.

An address period (not shown) and a sustain period (not shown) of asubfield SFn+1 may be the same as the address period PAn and the sustainperiod PSn of the subfield SFn.

A combination of main reset periods and auxiliary reset periods in aframe is not limited to any particular one. However, it is desirablethat a first subfield of a frame includes a main reset period and theother subfields of the frame include auxiliary reset periods.

FIG. 7 is a time dependent driving signals applied to electrodes in aPDP according to the driving method of another embodiment of the presentinvention. Referring to FIG. 7, driving signals in an address period anda sustain period of FIG. 7 are the same as those of the address periodand sustain period of FIG. 6 except that a main reset period PRnillustrated in FIG. 7 further includes a preset time period Tp. The mainreset period PRn includes the preset time period Tp, a first pulse timeperiod T1, and a second pulse time period T2.

During the preset time period Tp, a ramp pulse (a preset pulse) fallingfrom the level of the reference voltage Vg to a level of a fifth voltageVpnf is applied to the Y electrodes Y1 through Yn, the first voltage Vsis applied to the X electrodes X1 through Xn, and the reference voltageVg is applied to the A electrodes A1 through Am. The level of the fifthvoltage Vpnf can be the same as the level of the fourth voltage Vaf.

The first pulse time period T1 includes a first rising ramp pulse timeperiod T11 and a first falling ramp pulse time period T12. During thefirst rising ramp pulse time period T11, a voltage having a rising ramppulse waveform is applied to the Y electrodes Y1 through Yn. During thefirst falling ramp pulse time period T12, a voltage having a fallingramp pulse waveform is applied to the Y electrodes Y1 through Yn.

The second pulse time period T2 includes a second rising ramp pulse timeperiod T21 and a second falling ramp pulse time period T22. During thesecond rising ramp pulse time period T21, a voltage having a rising ramppulse waveform is applied to the Y electrodes Y1 through Yn. During thesecond falling ramp pulse time period T22, a voltage having a fallingramp pulse waveform is applied to the Y electrodes Y1 through Yn.

The preset time period Tp is set to create a sufficient number of wallcharges so that a discharge can occur during the first rising ramp pulsetime period T11 of the first pulse time period T1. In other words, inthe embodiment illustrated in FIG. 7, the main reset period PRn furtherincludes the preset time period Tp so that a weak discharge suitable foran address discharge subsequent to the first and second pulse timeperiod periods T1 and T2 can easily occur.

The second rising ramp pulse time period T21 of the second pulse timeperiod T2 is set to accumulate wall charges due to a weak discharge. Thesecond falling ramp pulse time period T22 of the second pulse timeperiod T2 is set so that the wall charges accumulated during the secondrising ramp pulse time period T21 of the second pulse time period T2 areerased due to a weak discharge so as to be suitable for the addressperiod PAn subsequent to the main reset period PRn.

The first rising ramp pulse time period T11 and the first falling ramppulse time period T12 of the first pulse time period T1 are prepared sothat a strong discharge may not occur during the second rising ramppulse time period T21 and the second falling ramp pulse time period T22of the second pulse time period T2.

According to the present invention, even in a situation where dischargecells abruptly change from an on state to an off state, a weak dischargeis induced during a reset period, so that an erroneous discharge can beprevented from occurring during a sustain period. A low discharge and anerroneous discharge in low-gray-level subfields can also be preventedfrom occurring in discharge cells that maintain an on state.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A method of driving a plasma display panel, which comprises Xelectrodes, Y electrodes, address electrodes, and discharge cells togenerate light, the method comprising: applying a main reset pulse tothe Y electrodes during a main reset period of a subfield to reset thedischarge cells, the step of applying the main reset pulse comprising:applying a pulse rising to a level of a first voltage and then fallingto a level of a second voltage during a first pulse time period; andapplying a pulse rising to a level of a third voltage and then fallingto a level of a fourth voltage during a second pulse time period, thefirst voltage being lower than the third voltage; applying an addressdata signal to the address electrodes during an address period to selectdischarge cells to be turned on; and alternatively applying a sustainpulse to the X electrodes and to the Y electrodes during a sustainperiod to generate a sustain discharge in the selected discharge cells.2. The method of claim 1, wherein the step of applying the main resetpulse further including: applying a pulse falling to a level of a fifthvoltage during a preset time period that is included in the main resetperiod.
 3. The method of claim 2, wherein the magnitude of the fifthvoltage is substantially the same as the magnitude of the fourthvoltage.
 4. The method of claim 1, wherein: the step of applying a pulserising to the level of the first voltage and then falling to the levelof the second voltage includes applying a pulse rising to the level ofthe first voltage from a level of a reference voltage; the step ofapplying a pulse rising to the level of the first voltage and thenfalling to the level of the second voltage includes applying a pulsefalling to the level of the second voltage from the level of thereference voltage; the step of applying a pulse rising to the level ofthe third voltage and then falling to the level of the fourth voltageincludes applying a pulse rising to the level of the third voltage froma level of a sixth voltage; and the step of applying a pulse rising tothe level of the third voltage and then falling to the level of thefourth voltage includes applying the pulse falling to the level of thefourth voltage from the level of the reference voltage.
 5. The method ofclaim 1, further comprising: applying an auxiliary reset pulse to the Yelectrodes during an auxiliary reset period of another subfield to resetthe discharge cells, a maximum voltage of the auxiliary reset pulsebeing lower than the third voltage.
 6. The method of claim 5, whereinthe step of applying the auxiliary reset pulse including a step selectedfrom the group consisting of: applying a pulse rising to a level of afirst auxiliary voltage; and applying a pulse falling to a level of asecond auxiliary voltage.
 7. The method of claim 1, further comprising:applying a reference voltage to the address electrodes during the mainreset period; and applying a seventh voltage to the X electrodes whileapplying a pulse falling to the level of the fourth voltage to the Yelectrodes during the second pulse time period.
 8. The method of claim1, further comprising: applying a seventh voltage to the X electrodesduring the address period; applying a selection pulse having a ninthvoltage to the Y electrodes during a selection time that is included inthe address period; and applying an eighth voltage to the Y electrodesduring a portion of the address period that is not included in theselection time, wherein the address data signal includes a data pulsehaving a reference voltage or a tenth voltage, the phase of the datapulse synchronizing with the phase of the selection pulse.
 9. The methodof claim 1, further comprising: applying a reference voltage to theaddress electrodes during the sustain period, wherein the sustain pulsehaving the first voltage.
 10. A plasma display panel device comprising:a plasma display panel comprising: a first substrate; a second substratefacing the first substrate; X electrodes and Y electrodes disposedbetween the first substrate and the second substrate; and addresselectrodes disposed between the first substrate and the secondsubstrate, the address electrodes crossing the X and Y electrodes,discharge cells being formed at intersections of the address electrodeswith the X and Y electrodes; and a panel driving unit applying a set ofdriving signals to the plasma display panel to drive the plasma displaypanel, the set of the driving signals comprising: a main reset pulseapplied to the Y electrodes during a main reset period of a subfield toreset the discharge cells, the main reset pulse comprising: a firstpulse rising to a level of a first voltage and then falling to a levelof a second voltage during a first pulse time period; and a second pulserising to a level of a third voltage and then falling to a level of afourth voltage during a second pulse time period, the first voltagebeing lower than the third voltage; an address data signal applied tothe address electrodes during an address period to select dischargecells to be turned on; and a sustain pulse alternately applied to the Xelectrodes and to the Y electrodes during a sustain period to generate asustain discharge in the selected discharge cells; and
 11. The PDP ofclaim 10, wherein the main reset pulse further includes a preset pulsefalling to a level of a fifth voltage during a preset time period thatis included in the main reset period.
 12. The PDP of claim 11, whereinthe magnitude of the fifth voltage is substantially the same as themagnitude of the fourth voltage.
 13. The PDP of claim 10, wherein: thefirst pulse rises to the level of the first voltage from a level of areference voltage; the first pulse falls to the level of the secondvoltage from the level of the reference voltage; the second pulse risesto the level of the third voltage from a level of a sixth voltage; andthe second pulse falls to the level of the fourth voltage from the levelof the reference voltage.
 14. The PDP of claim 10, wherein the set ofthe driving signals further comprises an auxiliary reset pulse appliedto the Y electrodes during an auxiliary reset period of another subfieldto reset the discharge cells, a maximum voltage of the auxiliary resetpulse being lower than the third voltage.
 15. The PDP of claim 14,wherein the auxiliary reset pulse includes a pulse selected from thegroup consisting of a first auxiliary pulse rising to a level of a firstauxiliary voltage and a second auxiliary pulse falling to a level of asecond auxiliary voltage.
 16. The PDP of claim 10, wherein: a referencevoltage is applied to the address electrodes during the main resetperiod; and a seventh voltage is applied to the X electrodes whileapplying a second pulse falling to the level of the fourth voltage. 17.The PDP of claim 10, wherein: a seventh voltage is applied to the Xelectrodes during the address period; a selection pulse having a ninthvoltage is applied to the Y electrodes during a selection time that isincluded in the address period; an eighth voltage is applied to the Yelectrodes during a portion of the address period that is not includedin the selection time; and the address data signal includes a data pulsehaving a reference voltage or a tenth voltage, the phase of the datapulse synchronizing with the phase of the selection pulse.
 18. The PDPof claim 10, wherein: a reference voltage is applied to the addresselectrodes during the sustain period; and the sustain pulse having thefirst voltage.